The present invention relates to vertical complementary metal oxide semiconductor transistors (CMOS), and more specifically, to anti-fuses manufactured alongside vertical CMOS transistors.
CMOS is used for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS designs may use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET uses electrons as the current carriers and with n-doped source and drain junctions. The pFET uses holes as the current carriers and with p-doped source and drain junctions. Vertical nFET or pFET transistors are an attractive option for technology scaling for 5 nm and beyond.
Programmable on-chip anti-fuses are needed in many semiconductor integrated circuit applications. Anti-fuses are an important part of a technology offering, as it is used for applications such as memory array redundancy, post-manufacture programming of circuits, and package identification coding.
An anti-fuse is an electrical device that performs the opposite function of a fuse. Whereas a fuse initially has a low resistance and is designed to permanently break an electrically conductive path (typically when the current through the path exceeds a specified limit), an anti-fuse initially has a high resistance and is designed to permanently create an electrically conductive path (typically when the voltage across the anti-fuse exceeds a certain level).
In some applications, it preferable to fabricate on-chip anti-fuses during vertical FinFET CMOS fabrication in order to minimize process cost and improve system integration. The breakdown voltage of conventional planar anti-fuses with a gate dielectric is too high. Also, planar anti-fuses use too much area compatible with current ground rules of 14 nm, 10 nm, or 7 nm technology nodes.
Therefore, there is a need for improved on-chip anti-fuses co-integrated with vertical stacked FinFET CMOS transistors.